From transistors
to compilers.

Von Neumann Bottleneck and Systolic Array Architecture: An Empirical Efficiency Comparison

Zenodo · doi:10.5281/zenodo.22038219 · science inquiry project, team of four · details KO

We built a 2×2 output-stationary systolic array from four Arduino Nano boards (ATmega328P, bit-banged GPIO links) and compared it against a sequential von Neumann–style baseline on the same matrix multiplications.

25%

less data movement (6K vs 8K moves)

295–326×

slower end to end

≈417×

higher cost per move (1,346.9 µs vs 3.23 µs)

1.0%

of grid time spent on actual MACs

Data reuse happened exactly as theory predicts, but moving each value between boards cost so much more than an on-chip access that the array lost overall. The result shows, in reverse, why processing elements have to live on the same chip.

KDAA: Korean Dubeolsik Acoustic Attack KO

Team research · my part: the acoustic front end · GitHub

Acoustic side-channel attacks on keyboards have been studied almost only on English QWERTY. On the Korean Dubeolsik layout, jamo compose into syllables, so the composition rules act as a nearly deterministic filter on a classifier’s mistakes. I build the CNN that classifies each keystroke’s log-mel spectrogram into 38 symbols (33 jamo and 5 special keys) and emits top-N probabilities to the decoder, targeting int8 inference on an ESP32-S3.